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?2006 silicon storage technology, inc. s71206-08-000 5/06 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. intel is a registered trademark of intel corporation. these specifications are subject to change without notice. data sheet features: ? lpc interface flash ? sst49lf020a: 256k x8 (2 mbit) ? conforms to intel lpc interface specification 1.0 ? flexible erase capability ? uniform 4 kbyte sectors ? uniform 16 kbyte overlay blocks ? top boot block protection: 16 kbyte ? chip-erase for pp mode only ? single 3.0-3.6v read and write operations ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption ? active read current: 6 ma (typical) ? standby current: 10 a (typical) ? fast sector-erase/byte-program operation ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? byte-program time: 14 s (typical) ? chip rewrite time: 4 seconds (typical) ? single-pulse program or erase ? internal timing generation ? two operational modes ? low pin count (lpc) interface mode for in-system operation ? parallel programming (pp) mode for fast production programming ? lpc interface mode ? 5-signal communication interface supporting byte read and write ? 33 mhz clock frequency operation ? wp# and tbl# pins provide hardware write protect for entire chip and/or top boot block ? standard sdp command set ? data# polling and toggle bit for end-of-write detection ? 5 gpi pins for system design flexibility ? 4 id pins for multi-chip selection ? parallel programming (pp) mode ? 11-pin multiplexed address and 8-pin data i/o interface ? supports fast programming in-system on programmer equipment ? cmos and pci i/o compatibility ? packages available ? 32-lead plcc ? 32-lead tsop (8mm x 14mm) ? all non-pb (lead-free) devices are rohs compliant product description the sst49lf020a flash memory device is designed to interface with the lpc bus for pc and internet appliance application in compliance with intel low pin count (lpc) interface specification 1.0. two interface modes are sup- ported: lpc mode for in-system operations and parallel programming (pp) mode to interface with programming equipment. the sst49lf020a flash memory device is manufactured with sst?s proprietary, high-performance superflash technology. the split-gate cell design and thick-oxide tun- neling injector atta in better reliability and manufacturability compared with alternate approaches. the sst49lf020a device significantly improves performance and reliability, while lowering power consumption. the sst49lf020a device writes (program or erase) with a single 3.0-3.6v power supply. it uses less energy during erase and pro- gram than alternative flash memory technologies. the total energy consumed is a function of the applied voltage, cur- rent and time of application. for any give voltage range, the superflash technology uses less current to program and has a shorter erase time; the total energy consumed during any erase or program operation is less than alternative flash memory technologies. the sst49lf020a product provides a maximum byte-program time of 20 sec. the entire memory can be erased and programmed byte-by- byte typically in 4 seconds when using status detection fea- tures such as toggle bit or data# polling to indicate the completion of program operation. the superflash technol- ogy provides fixed erase and program time, independent of the number of erase/program cycles that have per- formed. therefore the system software or hardware does not have to be calibrated or correlated to the cumulative number of erase cycles as is necessary with alternative flash memory technologies, whose erase and program time increase with accumulated erase/program cycles. to meet high density, surface mount requirements, the sst49lf020a device is offered in 32-lead tsop and 32- lead plcc packages. see figures 2 and 3 for pin assign- ments and table 1 for pin descriptions. 2 mbit lpc flash sst49lf020a sst49lf020a2mb lpc flash
2 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 table of contents product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 device memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 lpc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ce# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 lframe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 tbl#, wp# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 init#, rst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 system memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 response to invalid fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 abort mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write operation status detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 toggle bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 multiple device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 general purpose inputs register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 jedec id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 parallel programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 byte-program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 sector-erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 block-erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chip-erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 write operation status detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 data# polling (dq 7 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
data sheet 2 mbit lpc flash sst49lf020a 3 ?2006 silicon storage technology, inc. s71206-08-000 5/06 toggle bit (dq 6 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 data protection (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 software data protection (sdp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 software command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 absolute maximum stress ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 product ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 valid combinations for sst49lf020a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 packaging diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 list of figures figure 1: functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2: pin assignments for 32-lead plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3: pin assignments for 32-lead tsop (8mm x 14mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4: device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5: lpc read cycle waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6: lpc write cycle waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7: program command sequence (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8: data# polling command sequence (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9: toggle bit command sequence (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10: sector-erase command sequence (lpc mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11: block-erase command sequence (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 12: register readout command sequence (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 13: lclk waveform (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14: reset timing diagram (lpc mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15: output timing parameters (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16: input timing parameters (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 17: reset timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 18: read cycle timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19: write cycle timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 20: data# polling timing dia gram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 21: toggle bit timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 22: byte-program timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 23: sector-erase timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 figure 24: block-erase timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 25: chip-erase timing diagram (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 26: software id entry and read (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 27: software id exit (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 28: ac input/output reference waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 29: a test load example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 30: read flowchart (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 31: byte-program flowchart (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 32: erase command sequences flowchart (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 33: software product id command sequences flowchart (lpc mode) . . . . . . . . . . . . . . . . . . . . 42 figure 34: byte-program command sequences flowchart (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 35: wait options flowchart (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 36: software product id command sequences flowchart (pp mode) . . . . . . . . . . . . . . . . . . . . . 45 figure 37: erase command sequence flowchart (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 38: 32-lead plastic lead chip carrier (plcc) sst package code: nh . . . . . . . . . . . . . . . . . . . . 48 figure 39: 32-lead thin small outline package (tsop) 8mm x 14mm sst package code: wh . . . . . . 49
data sheet 2 mbit lpc flash sst49lf020a 5 ?2006 silicon storage technology, inc. s71206-08-000 5/06 list of tables table 1: pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2: product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3: address bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4: address decoding range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5: lpc read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6: lpc write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7: multiple device selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8: general purpose inputs register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9: memory map register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10: operation modes selection (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11: software command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12: dc operating characteristics (all interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13: recommended system power-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14: pin capacitance (vdd=3.3v, ta=25 c, f=1 mhz, other pins open) . . . . . . . . . . . . . . . . . . . . 28 table 15: reliability characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 16: clock timing parameters (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17: reset timing parameters, v dd =3.0-3.6v (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18: read/write cycle timing parameters, v dd =3.0-3.6v (lpc mode) . . . . . . . . . . . . . . . . . . . . . 30 table 19: ac input/output specifications (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 20: interface measurement condition parameters (lpc mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 21: read cycle timing parameters, v dd =3.0-3.6v (pp mode). . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 22: program/erase cycle timing parameters, v dd =3.0-3.6v (pp mode) . . . . . . . . . . . . . . . . . . . 33 table 23: reset timing parameters, v dd =3.0-3.6v (pp mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 24: revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 functional block diagram figure 1: functional block diagram 1206 b1.1 y-decoder i/o buffers and data latches address buffers & latches x-decoder superflash memory control logic lclk rst# ce# mode gpi[4:0] programmer interface wp# tbl# init# id[3:0] lframe# r/c# oe# we# a[10:0] dq[7:0] lad[3:0] lpc interface
data sheet 2 mbit lpc flash sst49lf020a 7 ?2006 silicon storage technology, inc. s71206-08-000 5/06 pin assignments figure 2: pin assignments for 32-lead plcc figure 3: pin assignments for 32-lead tsop (8mm x 14mm) 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7(gpi1) a6 (gpi0) a5 (wp#) a4 (tbl#) a3 (id3) a2 (id2) a1 (id1) a0 (id0) dq0 (lad0) mode (mode) nc (ce#) nc nc v dd (v dd ) oe# (init#) we# (lframe#) nc dq7 (res) 4 3 2 1 32 31 30 a8 (gpi2) a9 (gpi3) rst# (rst#) nc v dd (v dd ) r/c# (lclk) a10 (gpi4) 32-lead plcc top view 1206 32-plcc p1.0 14 15 16 17 18 19 20 dq1 (lad1) dq2 (lad2) v ss (v ss ) dq3 (lad3) dq4 (res) dq5 (res) dq6 (res) ( ) designates lpc mode nc nc nc nc (ce#) mode (mode) a10 (gpi4) r/c# (lclk) v dd (v dd ) nc rst# (rst#) a9 (gpi3) a8 (gpi2) a7 (gpi1) a6 (gpi0) a5 (wp#) a4 (tbl#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# (init#) we# (lframe#) v dd (v dd ) dq7 (res) dq6 (res) dq5 (res) dq4 (res) dq3 (lad3) v ss (v ss ) dq2 (lad2) dq1 (lad1) dq0 (lad0) a0 (id0) a1 (id1) a2 (id2) a3 (id3) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1206 32-tsop p2.0 standard pinout top view die up ( ) designates lpc mode
8 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 table 1: pin description symbol pin name type 1 interface functions pp lpc a 10 -a 0 address i x inputs for low-order addresses during read and write operations. addresses are internally latched during a write cycle. for the programming interface, these addresses are latched by r/c# and share the same pins as the high-order address inputs. dq 7 -dq 0 data i/o x to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# is high. oe# output enable i x to gate the data output buffers. we# write enable i x to control the write operations. mode interface mode select i x x this pin determines which interface is operational. when held high, programmer mode is enabled and when held low, lpc mode is enabled. this pin must be setup at power-up or before return from reset and not change during device oper- ation. this pin must be held high (v ih ) for pp mode and low (v il ) for lpc mode. init# initialize i x this is the second reset pin for in-system use. this pin is internally combined with the rst# pin; if this pin or rst# pin is driven low, identical operation is exhibited. id[3:0] identification inputs i x these four pins are part of the mechanism that allows multiple parts to be attached to the same bus. the strapping of these pins is used to identify the component.the boot device must have id[3:0]=0000 for all subsequent devices should use sequen- tial up-count strapping. these pins are internally pulled-down with a resistor between 20-100 k gpi[4:0] general purpose inputs i x these individual inputs can be used for additional board flexibility. the state of these pins can be read through lpc regi sters. these inputs should be at their desired state before the start of the pci clock cycle during which the read is attempted, and s hould remain in plac e until the end of th e read cycle. unused gpi pins must not be floated. tbl# top block lock i x when low, prevents programming to the boot block sectors at top of memory. when tbl# is high it disables hardware write protection for the top block sectors. this pin cannot be left unconnected. lad[3:0] address and data i/o x to provide lpc control signals, as well as addresses and command inputs/outputs data. lclk clock i x to provide a clock input to the control unit lframe# frame i x to indicate start of a data transf er operation; also used to abort an lpc cycle in progress. rst# reset i x x to reset the operation of the device wp# write protect i x when low, prevents programming to all but the highest addressable blocks. when wp# is high it disables hardware write protection for these blocks. this pin cannot be left unconnected. r/c# row/column select i x select for the programming interface, this pin determines whether the address pins are pointing to the row addresses, or to the column addresses. res reserved x these pins must be left unconnected. v dd power supply pwr x x to provide power supply (3.0-3.6v) v ss ground pwr x x circuit ground (0v reference) ce# chip enable i x this signal must be asserted to se lect the device. when ce# is low, the device is enabled. when ce# is high, the device is placed in low power standby mode. nc no connection i x x unconnected pins. t1.0 1206 1. i=input, o=output
data sheet 2 mbit lpc flash sst49lf020a 9 ?2006 silicon storage technology, inc. s71206-08-000 5/06 device memory maps figure 4: device memory map 3ffffh 3c000h 3bfffh 38000h 37fffh 34000h 33fffh 30000h 2ffffh 2c000h 2bfffh 28000h 27fffh 24000h 23fffh 20000h 1ffffh 1c000h 1bfffh 18000h 17fffh 14000h 13fffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 04000h 03fffh 300000 02fffh 02000h 01fffh 01000h 00fffh 00000h block 7 block 8 block 6 block 5 block 4 block 3 block 2 block 1 block 15 block 14 block 13 block 12 block 11 block 10 block 9 block 0 (16 kbyte) 1206 f02.0 wp# for block 0~14 tbl# 4 kbyte sector 1 4 kbyte sector 2 4 kbyte sector 3 4 kbyte sector 0 boot block
10 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 design considerations sst recommends a high frequency 0.1 f ceramic capac- itor to be placed as close as possible between v dd and v ss less than 1 cm away from the v dd pin of the device. additionally, a low frequency 4.7 f electrolytic capacitor from v dd to v ss should be placed within 5 cm of the v dd pin. if you use a socket for programming purposes add an additional 1-10 f next to each socket. product identification the product identification mode identifies the device as the sst49lf020a and manufacturer as sst. mode selection the sst49lf020a flash memory devices can operate in two distinct interface modes: the lpc mode and the parallel programming (pp) mode. the mode pin is used to set the interface mode selection. if the mode pin is set to logic high, the device is in pp mode. if the mode pin is set low, the device is in the lpc mode. the mode selection pin must be configured prior to device operation. the mode pin is inter- nally pulled down if the pin is left unconnected. in lpc mode, the device is configured to its host using standard lpc interface protocol. communication between host and the sst49lf020a occurs via the 4-bit i/o communication signals, lad [3:0] and lframe#. in pp mode, the device is programmed via an 11-bit address and an 8-bit data i/o parallel signals. the address inputs are multiplexed in row and column selected by control signal r/c# pin. the row addresses are mapped to the lower internal addresses (a 10-0 ), and the column addresses are mapped to the higher internal addresses (a ms-11 ). see figure 4, the device memory map, for address assignments. lpc mode device operation the lpc mode uses a 5-signal communication interface, a 4-bit address/data bus, lad[3:0], and a control line, lframe#, to control operations of the sst49lf020a. cycle type operations such as memory read and memory write are defined in intel low pin count interface specifi- cation, revision 1.0. jedec standard sdp (software data protection) program and erase commands sequences are incorporated into the standard lpc mem- ory cycles. see figures 7 through 12 for command sequences. lpc signals are transmitted via the 4-bit address/data bus (lad[3:0]), and follow a particular sequence, depending on whether they are read or write operations. lpc memory read and write cycle is defined in tables 5 and 6. both lpc read and write operations start in a similar way as shown in figures 5 and 6. the host (which is the term used here to describe the device driving the memory) asserts lframe# for one or more clocks and drives a start value on the lad[3:0] bus. at the beginning of an operation, the host may hold the lframe# active for several clock cycles, and even change the start value. the lad[3:0] bus is latched every rising edge of the clock. on the cycle in which lframe# goes inactive, the last latched value is taken as the start value. ce# must be asserted one cycle before the start cycle to select the sst49lf020a for read and write operations. once the sst49lf020a identify the operation as valid (a start value of all zeros), it next expects a nibble that indi- cates whether this is a memory read or write cycle. once this is received, the device is now ready for the address cycles. the lpc protocol supports a 32-bit address phase. the sst49lf020a encode id and register space access in the address field. see table 3 for address bits definition. for write operation the data cycle will follow the address cycle, and for read operation tar and sync cycles occur between the address and data cycles. at the end of every operation, the control of the bus must be returned to the host by a 2-clock tar cycle. table 2: product identification address data manufacturer?s id 0000h bfh device id sst49lf020a 0001h 52h t2.2 1206 table 3: address bits definition a 31 : a 23 a 22 a 21 : a 18 a 17 :a 0 1111 1111 1b 1 = memory access 0 = register access id[3:0] 1 1. see table 7 for multiple device selection configuration. device memory address t3.0 1206
data sheet 2 mbit lpc flash sst49lf020a 11 ?2006 silicon storage technology, inc. s71206-08-000 5/06 ce# the ce# pin, enables and disables the sst49lf020a, controlling read and write access of the device. to enable the sst49lf020a, the ce# pin must be driven low one clock cycle prior to lframe# being driven low. the device will enter standby mode when internal write operations are completed and ce# is high. lframe# the lframe# signifies the start of a (frame) bus cycle or the termination of an undesir ed cycle. asserting lframe# for one or more clock cycle and driving a valid start value on lad[3:0] will initiate devi ce operation. the device will enter standby mode when internal operations are com- pleted and lframe# is high. tbl#, wp# the top boot lock (tbl#) and write protect (wp#) pins are provided for hardware write protection of device mem- ory. the tbl# pin is used to write-protect 4 boot sectors (16 kbyte). the wp# pin write protects the remaining sec- tors in the flash memory. an active low signal at the tbl# pin prevents program and erase operations of the top boot sectors. when tbl# pin is held high, the write protection of the top boot sectors is dis- abled. the wp# pin serves the same function for the remaining sectors of the device memory. the tbl# and wp# pins write protection functions operate independently of one another. both tbl# and wp# pins must be set to their required pro- tection states prior to starting a program or erase opera- tion. a logic level change occurring at the tbl# or wp# pin during a program or erase operation could cause unpre- dictable results. init#, rst# a v il on init# or rst# pin initiates a device reset. init# and rst# pins have the same function internally. it is required to drive init# or rst# pins low during a system reset to ensure proper cpu initialization. during a read operation, driving init# or rst# pins low deselects the device and places the output drivers, lad[3:0], in a high- impedance state. the reset signal must be held low for a minimal duration of time t rstp . a reset latency will occur if a reset procedure is performed during a program or erase operation. see table 17, reset timing parameters for more information. a device reset during an active program or erase will abort the operati on and memory contents may become invalid due to data being altered or corrupted from an incomplete erase or program operation. system memory mapping the lpc interface protocol has address length of 32-bit or 4 gbyte. the sst49lf020a will respond to addresses in the range as specified in table 4. refer to ?multiple device selection? section for more detail on strapping multiple sst49lf020a devices to increase memory densities in a system and ?registers? section on valid register addresses. table 4: address decoding range id strapping device access address range memory size device #0 - 15 memory access ffff ffffh : ffc0 0000h 4 mbyte register access ffbf ff ffh : ff80 0000h 4 mbyte t4.0 1206
12 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 5: lpc read cycle waveform table 5: lpc read cycle clock cycle field name field contents lad[3:0] 1 lad[3:0] direction comments 1 start 0000 in lframe# must be active (low) for the part to respond. only the last start field (before lframe# transitions high) should be rec- ognized. 2 cyctype + dir 010x in indicates the type of cycle. bi ts 3:2 must be ?01b? for memory cycle. bit 1 indicates the type of transfer ?0? for read. bit 0 is reserved. 3-10 address yyyy in address phase for memory cycle. lpc protocol supports a 32- bit address phase. yyyy is one nibb le of the entire address. addresses are transferred most-significant nibble fist. see table 3 for address bits definition and ta b l e 4 for valid memory address range. 11 tar0 1111 in then float in this clock cycle, the host has driven the bus to all 1s and then floats the bus. this is the first part of the bus ?turnaround cycle.? 12 tar1 1111 (float) float then out the sst49lf020a take s control of the bus during this cycle 13 sync 0000 out the sst49lf020a outputs the value 0000b indicating that data will be available duri ng the next clock cycle. 14 data zzzz out this field is the least- significant nibble of the data byte. 15 data zzzz out this field is the most-significant nibble of the data byte. 16 tar0 1111 out then float in this clock cycle, the sst49lf020a has driven the bus to all 1s and then floats the bus. this is the first part of the bus ?turn- around cycle.? 17 tar1 1111 (float) float then in the host takes control of the bus during this cycle t5.0 1206 1. field contents are valid on the ri sing edge of the present clock cycle. 1206 f06.0 lclk ce# lframe# lad[3:0] 0000b 010xb a[23:20] a[19:16] a[3:0] a[7:4] a[11:8] a[15:12] 1111b tri-state 2 clocks tar0 load address in 8 clocks address 1 clock 1 clock start cyctype + dir ta r 1 clock sync data data out 2 clocks 0000b d[7:4] d[3:0] a[31:28] a[27:24] tar1
data sheet 2 mbit lpc flash sst49lf020a 13 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 6: lpc write cycle waveform table 6: lpc write cycle clock cycle field name field contents lad[3:0] 1 lad[3:0] direction comments 1 start 0000 in lframe# must be active (low) for the part to respond. only the last start field (before lframe# transitions high) should be recognized. 2 cyctype + dir 011x in indicates the type of cycl e. bits 3:2 must be ?01b? for memory cycle. bit 1 indicates the type of transfer ?1? for write. bit 0 is reserved. 3-10 address yyyy in address phase for me mory cycle. lpc protocol sup- ports a 32-bit address phase. yyyy is one nibble of the entire address. addresses are transferred most- significant nibble first. see table 3 for address bits def- inition and ta b l e 4 for valid memory address range. 11 data zzzz in this field is the least- significant nibble of the data byte. 12 data zzzz in this field is the most-s ignificant nibble of the data byte. 13 tar0 1111 in then float in this clock cycle, the host has driven the bus to all ?1?s and then floats the bus. this is the first part of the bus ?turnaround cycle.? 14 tar1 1111 (float) float then out the sst49lf020a takes control of the bus during this cycle. 15 sync 0000 out the sst49lf020a outputs the values 0000, indicat- ing that it has received data or a flash command. 16 tar0 1111 out then float in this clock cycle, the sst49lf020a has driven the bus to all ?1?s and then floats the bus. this is the first part of the bus ?turnaround cycle.? 17 tar1 1111 (float) float then in host resumes control of the bus during this cycle. t6.0 1206 1. field contents are valid on the ri sing edge of the present clock cycle. 1206 f07.0 lframe# lad[3:0] 0000b 011xb a[23:20] a[19:16] a[3:0] a[7:4] a[11:8] a[15:12] 1111b tri-state 2 clocks tar0 load address in 8 clocks address 1 clock 1 clock start cyctype + dir ta r 1 clock sync data load data in 2 clocks 0000b d[7:4] d[3:0] lclk ce# a[31:28] a[27:24] data tar1
14 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 response to invalid fields during lpc read/write operations, the sst49lf020a will not explicitly indicate that it has received invalid field sequences. the response to specific invalid fields or sequences is as follows: address out of range: the sst49lf020a will only response to address range as specified in table 4. id mismatch : id information is included in every address cycle. the sst49lf020a will co mpare id bits in the address field with the hardware id strapping. if there is a mis-match, the device will ignore the cycle. see multiple device selection section for details. once valid start, cyctype + dir, valid address range and id bits are received, the sst49lf020a will always complete the bus cycle. however, if the device is busy per- forming a flash erase or program operation, no new inter- nal write command (memory write or register write) will be executed. as long as the states of lad[3:0] and lad[4] are known, the response of the sst49lf020a to signals received during the lpc cycle should be predictable. abort mechanism if lframe# is driven low for one or more clock cycles after the start of an lpc cycle, the cycle will be terminated. the host may drive the lad[3:0] with ?1111b? (abort nibble) to return the interface to ready mode. the abort only affects the current bus cycle. for a multi-cycle command sequence, such as the erase or program sdp commands, abort doesn?t interrupt the entire command sequence, but only the current bus cycle of the command sequence. the host can re-send the bus cycle and continue the sdp command sequence after the device is ready again. write operation status detection the sst49lf020a device provides two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the soft- ware detection includes two status bits: data# polling, d[7], and toggle bit, d[6]. the end-of-write detection mode is incorporated into the lpc read cycle. the actual comple- tion of the nonvolatile write is asynchronous with the sys- tem; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an errone- ous result, i.e., valid data may appear to conflict with either d[7] or d[6]. in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data# polling when the sst49lf020a device is in the internal program operation, any attempt to r ead d[7] will produce the com- plement of the true data. once the program operation is completed, d[7] will produce true data. note that even though d[7] may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase opera- tion, any attempt to read d[7] will produce a ?0?. once the internal erase operation is co mpleted, d[7] will produce a ?1?. proper status will not be given using data# polling if the address is in the invalid range. toggle bit during the internal program or erase operation, any consec- utive attempts to read d[6] will produce alternating 0s and 1s, i.e., toggling between 0 and 1. when the internal pro- gram or erase operation is completed, the toggling will stop.
data sheet 2 mbit lpc flash sst49lf020a 15 ?2006 silicon storage technology, inc. s71206-08-000 5/06 multiple device selection multiple lpc flash devices may be strapped to increase memory densities in a system. the four id pins, id[3:0], allow up to 16 devices to be attached to the same bus by using different id strapping in a system. bios support, bus loading, or the attaching bridge may limit this number. the boot device must have an id of 0 (determined by id[3:0]); subsequent devices use incremental numbering. equal density must be used with multiple devices. when used as a boot device, id[3:0] must be strapped as 0000; all subsequent devices should use a sequential up- count strapping (i.e. 0001, 0010, 0011, etc.). with the hard- ware strapping, id information is included in every lpc address memory cycle. the id bits in the address field are inverse of the hardware strapping. the address bits [a 21 :a 18 ] are used to select the device with proper ids. see table 7 for ids. the sst49lf 020a will compare these bits with id[3:0]?s strapping values. if there is a mismatch, the device will ignore the re minder of the cycle. registers there are two registers available on the sst49lf020a, the general purpose inputs registers (gpi_reg) and the jedec id registers. since multiple lpc memory devices may be used to increase memory densities, these registers appear at its respective address location in the 4 gbyte system memory map. unused register locations will read as 00h. any attempt to read registers during internal write operation will respond as ?write operation status detection? (data# polling or toggle bit). any attempt to write any reg- isters during internal write operation will be ignored. table 9 lists gpi_reg and jedec id address locations for sst49lf020a with its respective device strapping. table 7: multiple device selection configuration device # hardware strapping address bits decoding id[3:0] a 21 a 20 a 19 a 18 0 (boot device) 0000 1 1 1 1 100011110 200101101 300111100 401001011 501011010 601101001 701111000 810000111 910010110 10 1010 0 1 0 1 11 1011 0 1 0 0 12 1100 0 0 1 1 13 1101 0 0 1 0 14 1110 0 0 0 1 15 1111 0 0 0 0 t7.2 1206 table 8: general purpose inputs register bit function pin # 32-plcc 32-tsop 7:5 reserved - - 4 gpi[4] reads status of general purpose input pin 30 6 3 gpi[3] reads status of general purpose input pin 311 2 gpi[2] reads status of general purpose input pin 412 1 gpi[1] reads status of general purpose input pin 513 0 gpi[0] reads status of general purpose input pin 614 t8.0 1206
16 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 general purpose inputs register the gpi_reg (general purpose inputs register) passes the state of gpi[4:0] pins at power-up on the sst49lf020a. it is recommended that the gpi[4:0] pins be in the desired state before lframe# is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle. there is no default value since this is a pass-through register. see the general purpose inputs register table for the gpi_reg bits and function, and table 9 for memory address locations for its respective device strapping. jedec id registers the jedec id registers identify the device as sst49lf020a and manufacturer as sst in lpc mode. see table 9 for memory address locations for its respective jedec id location. table 9: memory map register addresses device # hardware strapping id[3:0] gpi_reg jedec id manufacturer device 0 (boot device) 0000 ffbc 0100h ffbc 0000h ffbc 0001h 1 0001 ffb8 0100h ffb8 0000h ffb8 0001h 2 0010 ffb4 0100h ffb4 0000h ffb4 0001h 3 0011 ffb0 0100h ffb0 0000h ffb0 0001h 4 0100 ffac 0100h ffac 0000h ffac 0001h 5 0101 ffa8 0100h ffa8 0000h ffa8 0001h 6 0110 ffa4 0100h ffa4 0000h ffa4 0001h 7 0111 ffa0 0100h ffa0 0000h ffa0 0001h 8 1000 ff9c 0100h ff9c 0000h ff9c 0001h 9 1001 ff98 0100h ff98 0000h ff98 0001h 10 1010 ff94 0100h ff94 0000h ff94 0001h 11 1011 ff90 0100h ff90 0000h ff90 0001h 12 1100 ff8c 0100h ff8c 0000h ff8c 0001h 13 1101 ff88 0100h ff88 0000h ff88 0001h 14 1110 ff84 0100h ff84 0000h ff84 0001h 15 1111 ff80 0100h ff80 0000h ff80 0001h t9.0 1206
data sheet 2 mbit lpc flash sst49lf020a 17 ?2006 silicon storage technology, inc. s71206-08-000 5/06 parallel programming mode device operation commands are used to initiate the memory operation func- tions of the device. the data portion of the software com- mand sequence is latched on the rising edge of we#. during the software command sequence the row address is latched on the falling edge of r/c# and the column address is latched on the rising edge of r/c#. reset driving the rst# low will initiate a hardware reset of the sst49lf020a. see table 23 for reset timing parameters and figure 17 for reset timing diagram. read the read operation of the sst49lf020a device is con- trolled by oe#. oe# is the output control and is used to gate data from the output pins. refer to the read cycle tim- ing diagram, figure 18, for further details. byte-program operation the sst49lf020a device is programmed on a byte-by- byte basis. before programming, one must ensure that the sector in which the byte is programmed is fully erased. the byte-program operation is initiated by executing a four-byte command load sequence for software data protection with address (ba) and data in the last byte sequence. during the byte-program operation, the row address (a 10 -a 0 ) is latched on the falling edge of r/c# and the column address (a 21 -a 11 ) is latched on the rising edge of r/c#. the data bus is latched on the rising edge of we#. the program operation, once initiated, will be completed, within 20 s. see figure 22 for program operation timing diagram and figure 34 for its flowchart. during the program operation, the only valid reads are data# polling and toggle bit. dur- ing the internal program operation, the host is free to per- form additional tasks. any commands written during the internal program operation will be ignored. sector-erase operation the sector-erase operation allows the system to erase the device on a sector-by-sector basis. the sector archi- tecture is based on uniform sector size of 4 kbyte. the sector-erase operation is initiated by executing a six-byte command load sequence for software data protection with sector-erase command (30h) and sector address (sa) in the last bus cycle. the internal erase operation begins after the sixth we# pulse. the end-of-erase can be determined using either data# polling or toggle bit methods. see figure 23 for sector-erase timing wave- forms. any commands written during the sector-erase operation will be ignored. block-erase operation the block-erase operation allows the system to erase the device in 16 kbyte uniform block size for the sst49lf020a. the block-erase operation is initiated by executing a six-byte command load sequence for software data protection with block-erase command (50h) and block address. the internal block-erase operation begins after the sixth we# pulse. the end-of-erase can be deter- mined using either data# polling or toggle bit methods. see figure 24 for block-erase timing waveforms. any com- mands written during the bl ock-erase operation will be ignored. chip-erase operation the sst49lf020a devices provide a chip-erase opera- tion, which allows the user to erase the entire memory array to the ?1s? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte software data protection command sequence with chip-erase command (10h) with address 5555h in the last byte sequence. the internal erase operation begins with the rising edge of the sixth we#. during the internal erase operation, the only valid read is toggl e bit or data# polling. see table 11 for the command sequence, figure 25 for chip-erase timing diagram, and figure 37 for the flowchart. any commands written during the chip-erase operation will be ignored.
18 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 write operation status detection the sst49lf020a devices provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the soft- ware detection includes two status bits: data# polling d[7] and toggle bit d[6]. the end-of-write detection mode is enabled after the rising edge of we# which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either d[7] or d[6]. in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid. data# polling (dq 7 ) when the sst49lf020a device is in the internal program operation, any attempt to read dq 7 will produce the com- plement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase opera- tion, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# pulse for program operation. for sector-, block-, or chip-erase, the data# polling is valid after the rising edge of sixth we# pulse. see figure 20 for data# polling timing diagram and figure 35 for a flowchart. proper status will not be given using data# polling if the address is in the invalid range. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. when the internal program or erase operation is completed, the toggling will stop. the device is then ready for the next operation. the toggle bit is valid after the rising edge of fourth we# pulse for program operation. for sector-, block-, or chip-erase, the toggle bit is valid after the rising edge of sixth we# pulse. see figure 21 for toggle bit timing diagram and fig- ure 35 for a flowchart. table 10: operation modes selection (pp mode) mode rst# oe# we# dq address read v ih v il v ih d out a in program v ih v ih v il d in a in erase v ih v ih v il x 1 1. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase reset v il x x high z x write inhibit v ih x v il x x v ih high z/d out high z/d out x x product identification v ih v il v ih manufacturer?s id (bfh) device id 2 2. device id = 52h for sst49lf020a see table 11 t10.2 1206
data sheet 2 mbit lpc flash sst49lf020a 19 ?2006 silicon storage technology, inc. s71206-08-000 5/06 data protection (pp mode) the sst49lf020a devices provide both hardware and software features to protect nonvolatile data from inadvert- ent writes. hardware data protection noise/glitch protection: a we# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, we# high will inhibit the write operation. this prevents inadvertent writes during power-up or power-down. software data protection (sdp) the sst49lf020a provide the jedec approved software data protection scheme for all data alteration operation, i.e., program and erase. any program operation requires the inclusion of a series of three-byte sequence. the three- byte load sequence is used to initiate the program opera- tion, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power- down. any erase operation requires the inclusion of a six- byte load sequence.
20 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 software comm and sequence table 11: software command sequence command sequence 1st 1 cycle 1. lpc mode use consecutive write cycles to complete a command sequence; pp mode use consecut ive bus cycles to complete a command sequence. 2nd 1 cycle 3rd 1 cycle 4th 1 cycle 5th 1 cycle 6th 1 cycle addr 2 2. yyyy = a[31:16]. in lpc mode, during sdp command sequence, yyyy must be within memory address range specified in table 4. in pp mode, yyyy can be v il or v ih , but no other value. data addr 2 data addr 2 data addr 2 data addr 2 data addr 2 data byte-program yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h a0h pa 3 3. pa = program byte address data sector-erase yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 80h yyyy 5555h aah yyyy 2aaah 55h sa x 4 4. sa x for sector-erase address 30h block-erase yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 80h yyyy 5555h aah yyyy 2aaah 55h ba x 5 5. ba x for block-erase address 50h chip-erase 6 6. chip-erase is supported in pp mode only yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 80h yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 10h software id entry yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h 90h read id 7 7. sst manufacturer?s id = bfh, is read with a 0 = 0. with a 17 -a 1 = 0; sst49lf020a device id = 52h, is read with a 0 = 1. software id exit 8 8. both software id exit operations are equivalent xxxx xxxxh f0h software id exit 8 yyyy 5555h aah yyyy 2aaah 55h yyyy 5555h f0h t11.1 1206
data sheet 2 mbit lpc flash sst49lf020a 21 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 7: program command sequence (lpc mode) 1206 f08.0 lclk lframe# lad[3:0] 0000b 011xb a[23:20] a[19:16] 0101b 0101b 0101b 1010b 0101b 1010b tri-state ta r load address "yyyy 5555h" in 8 clocks write the 1st command to the device in lpc mode. address 1 1 clock 1 clock 1st start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "aah" in 2 clocks 1111b 0000b lclk lframe# lad[3:0] 0000b 011xb a[23:20] a[19:16] 1010b 1010b 1010b 0101b 0010b 0101b tri-state ta r load address "yyyy 2aaah" in 8 clocks write the 2nd command to the device in lpc mode. address 1 1 clock 1 clock 2nd start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "55h" in 2 clocks 1111b 0000b lclk lframe# load address "yyyy 5555h" in 8 clocks write the 3rd command to the device in lpc mode. 1 clock 1 clock 3rd start 1 clock 1 clock 2 clocks load data "a0h" in 2 clocks lclk lframe# lad[3:0] 0000b 011xb a[23:20] a[19:16] a[11:8] a[7:4] a[3:0] d[7:4] a[15:12] d[3:0] tri-state ta r load ain in 8 clocks write the 4th command (target locations to be programmed) to the device in lpc mode. address 1 1 clock 1 clock 4th start memory write cycle ta r sync data internal program start internal program start 1 clock 2 clocks load data in 2 clocks 1111b 0000b ce# ce# ce# ce# lad[3:0] 0000b 011xb a[23:20] a[19:16] 0101b 0101b 0101b 1010b 0101b 0000b tri-state ta r address 1 ta r sync data start next command 1111b 0000b a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] note: 1. address must be within memory address range specified in table 4.
22 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 8: data# polling command sequence (lpc mode) 1206 f09.0 0000b 011xb a[11:8] a[7:4] a[3:0] dn[7:4] a[15:12] d[3:0] tri-state ta r load address in 8 clocks write the last command (program or erase) to the device in lpc mode. address 1 1 clock 1 clock 1st start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data in 2 clocks 1111b 0000b 0000b lad[3:0] read the dq 7 to see if internal write complete or not. lclk lframe# lad[3:0] 0000b 010xb a[11:8] a[7:4] a[3:0] d7,xxx a[15:12] xxxxb tri-state ta r load address in 8 clocks when internal write complete, the dq 7 will equal to d7. address 1 1 clock 1 clock start memory read cycle ta r sync data next start 1 clock data out 2 clocks 1 clock 2 clocks 1111b 0000b 0000b lframe# lclk 0000b 010xb a[11:8] a[7:4] a[3:0] d7#,xxx a[15:12] xxxxb tri-state ta r load address in 8 clocks address 1 1 clock 1 clock start memory read cycle ta r sync data next start 1 clock data out 2 clocks 1 clock 2 clocks 1111b 0000b 0000b ce# ce# a[23:20] a[19:16] a[23:20] a[19:16] a[23:20] a[19:16] lframe# lad[3:0] lclk ce# a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] note: 1. address must be within memory address range specified in table 4.
data sheet 2 mbit lpc flash sst49lf020a 23 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 9: toggle bit command sequence (lpc mode) 1206 f10.0 lframe# lad[3:0] 0000b 011xb a[11:8] a[7:4] a[3:0] d[7:4] a[15:12] d[3:0] tri-state ta r load address in 8 clocks write the last command (program or erase) to the device in lpc mode. address 1 1 clock 1 clock 1st start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data in 2 clocks 1111b 0000b 0000b lclk lframe# lad[3:0] 0000b 010xb x,d6#,xxb xxxxb tri-state ta r load address in 8 clocks read the dq 6 to see if internal write complete or not. address 1 1 clock 1 clock start memory read cycle ta r sync data next start 1 clock data out 2 clocks 1 clock 2 clocks 1111b 0000b 0000b lclk lframe# lad[3:0] 0000b 010xb x,d6,xxb xxxxb tri-state ta r load address in 8 clocks when internal write complete, the dq 6 will stop toggle. address 1 1 clock 1 clock start memory read cycle ta r sync data next start 1 clock data out 2 clocks 1 clock 2 clocks 1111b 0000b 0000b ce# ce# lclk ce# a[11:8] a[7:4] a[3:0] a[15:12] a[11:8] a[7:4] a[3:0] a[15:12] a[23:20] a[19:16] a[23:20] a[19:16] a[23:20] a[19:16] a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] note: 1. address must be within memory address range specified in table 4.
24 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 10: sector-erase command sequence (lpc mode) 1206 f11.0 lframe# lad[3:0] 0000b 011xb 0101b 0101b 0101b 1010b 0101b 1010b tri-state ta r load address "yyyy 5555h" in 8 clocks write the 1st command to the device in lpc mode. address 1 1 clock 1 clock 1st start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "aah" in 2 clocks 1111b 0000b lclk lframe# lad[3:0] 0000b 011xb 1010b 1010b 1010b 0101b 0010b 0101b tri-state ta r load address "yyyy 2aaah" in 8 clocks write the 2nd command to the device in lpc mode. address 1 1 clock 1 clock 2nd start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "55h" in 2 clocks 1111b 0000b lclk lframe# lad[3:0] 0000b 011xb 0101b 0101b 0101b 1000b 0101b 0000b tri-state ta r load address "yyyy 5555h" in 8 clocks write the 3rd command to the device in lpc mode. address 1 1 clock 1 clock 3rd start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "80h" in 2 clocks 1111b 0000b lclk lframe# lad[3:0] 0000b 011xb 0101b 0101b 0101b 1010b 0101b 1010b tri-state ta r load address "yyyy 5555h" in 8 clocks write the 4th command to the device in lpc mode. address 1 1 clock 1 clock 4th start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "aah" in 2 clocks 1111b 0000b lclk lframe# lad[3:0] 0000b 011xb 1010b 1010b 1010b 0101b 0010b 0101b xxxxb xxxxb xxxxb 0011b sa x 0000b tri-state ta r load address "yyyy 2aaa" in 8 clocksh load sector address in 8 clocks write the 5th command to the device in lpc mode. address 1 1 clock 1 clock 5th memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "55h" in 2 clocks load data ?30? in 2 clocks 1111b 0000b lclk lframe# lad[3:0] 0000b 011xb tri-state ta r write the 6th command (target sector to be erased) to the device in lpc mode. sa x = sector address address 1 1 clock 1 clock 6th start memory write cycle ta r sync data internal erase start internal erase start 1 clock 2 clocks 1111b 0000b ce# ce# ce# ce# ce# lclk ce# a[23:20] a[19:16] a[23:20] a[19:16] a[23:20] a[19:16] a[23:20] a[19:16] a[23:20] a[19:16] a[23:20] a[19:16] a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] note: 1. address must be within memory address range specified in table 4.
data sheet 2 mbit lpc flash sst49lf020a 25 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 11: block-erase command sequence (lpc mode) 1206 f12.0 lframe# lad[3:0] 0000b 011xb a[23:20] a[19:16] 0101b 0101b 0101b 1010b 0101b 1010b tri-state ta r load address "yyyy 5555h" in 8 clocks write the 1st command to the device in lpc mode. address 1 1 clock 1 clock 1st start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "aah" in 2 clocks 1111b 0000b lclk lframe# lad[3:0] 0000b 011xb a[23:20] a[19:16] 1010b 1010b 1010b 0101b 0010b 0101b tri-state ta r load address "yyyy 2aaah" in 8 clocks write the 2nd command to the device in lpc mode. address 1 1 clock 1 clock 2nd start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "55h" in 2 clocks 1111b 0000b lclk lframe# lad[3:0] 0000b 011xb a[23:20] a[19:16] 0101b 0101b 0101b 1000b 0101b 0000b tri-state ta r load address "yyyy 5555h" in 8 clocks write the 3rd command to the device in lpc mode. address 1 1 clock 1 clock 3rd start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "80h" in 2 clocks 1111b 0000b lclk lframe# lad[3:0] 0000b 011xb a[23:20] a[19:16] 0101b 0101b 0101b 1010b 0101b 1010b tri-state ta r load address "yyyy 5555h" in 8 clocks write the 4th command to the device in lpc mode. address 1 1 clock 1 clock 4th start memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "aah" in 2 clocks 1111b 0000b lclk lframe# lad[3:0] 0000b 011xb a[23:20] a[19:16] 1010b 1010b 1010b 0101b 0010b 0101b a[19:16] xxxxb xxxxb xxxxb 0101b ba x 0000b tri-state ta r load address "yyyy 2aaah" in 8 clocks load block address in 8 clocks write the 5th command to the device in lpc mode. address 1 1 clock 1 clock 5th memory write cycle ta r sync data start next command 1 clock 1 clock 2 clocks load data "55h" in 2 clocks load data ?50? in 2 clocks 1111b 0000b lclk lframe# lad[3:0] 0000b 011xb a[23:20] tri-state ta r write the 6th command (target sector to be erased) to the device in lpc mode. ba x = block address address 1 1 clock 1 clock 6th start memory write cycle ta r sync data internal erase start internal erase start 1 clock 2 clocks 1111b 0000b ce# ce# ce# ce# ce# lclk ce# a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] a[31:28] a[27:24] note: 1. address must be within memory address range specified in table 4.
26 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 12: register readout command sequence (lpc mode) 0000b 010xb 1111b tri-state ta r load address in 8 clocks address 1 1 clock 1 clock start memory read cycle ta r sync data start next 1 clock data out 2 clocks 1 clock 2 clocks 0000b d[3:0] d[7:4] 0000b 1206 f13.0 lframe# lad[3:0] lclk ce# a[23:20] a[19:16] a[11:8] a[7:4] a[3:0] a[15:12] a[31:28] a[27:24] note: 1. see table 9 for register addresses.
data sheet 2 mbit lpc flash sst49lf020a 27 ?2006 silicon storage technology, inc. s71206-08-000 5/06 electrical specifications the ac and dc specifications for the lpc interface si gnals (la0[3:0], lframe, lclck and rst#) as defined in section 4.2.2.4 of the pci local bus specification, rev. 2.1. refer to table 12 for the dc voltage and current speci- fications. refer to tables 16 through 19 and tables 21 thro ugh 23 for the ac timing specifications for clock, read, write, and reset operations. absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this datasheet is not implied. ex posure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d.c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0 .5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (ta=25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds 1. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 2. outputs shorted for no more than one second. no more than one output shorted at a time. operating range range ambient temp v dd commercial 0c to +85c 3.0-3.6v ac conditions of test input rise/fall time . . . . . . . . . . . . . . . 3 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 28 and 29
28 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 dc characteristics table 12: dc operating characteristics (all interfaces) symbol parameter limits test conditions min max units i dd 1 1. i dd active while a read or write (program or erase) operation is in progress. active v dd current lclk (lpc mode) and address input (pp mode) =v ilt /v iht at f=33 mhz (lpc mode) or 1/ trc min (pp mode) all other inputs=v il or v ih read 12 ma all outputs = open, v dd =v dd max write 24 ma see note 2 2. for pp mode: oe# = we# = v ih; for lpc mode: f = 1/t rc min , lframe# = v ih, ce# = v il. i sb standby v dd current (lpc interface) 100 a lclk (lpc mode) and address input (pp mode) =v ilt /v iht at f=33 mhz (lpc mode) or 1/ trc min (pp mode) lframe#=0.9 v dd , f=33 mhz, ce#=0.9 v dd , v dd =v dd max, all other inputs 0.9 v dd or 0.1 v dd i ry 3 3. the device is in ready mode w hen no activity is on the lpc bus. ready mode v dd current (lpc interface) 10 ma lclk (lpc mode) and address input (pp mode) =v ilt /v iht at f=33 mhz (lpc mode) or 1/ trc min (pp mode) lframe#=v il , f=33 mhz, v dd =v dd max all other inputs 0.9 v dd or 0.1 v dd i i input current for mode and id[3:0] pins 200 a v in =gnd to v dd , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v ihi init# input high voltage 1.1 v dd +0.5 v v dd =v dd max v ili init# input low voltage -0.5 0.4 v v dd =v dd min v il input low voltage -0.5 0.3 v dd vv dd =v dd min v ih input high voltage 0.5 v dd v dd +0.5 v v dd =v dd max v ol output low voltage 0.1 v dd vi ol =1500 a, v dd =v dd min v oh output high voltage 0.9 v dd vi oh =-500 a, v dd =v dd min t12.2 1206 table 13: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t13.0 1206 table 14: pin capacitance (v dd =3.3v, ta=25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o =0v 12 pf c in 1 input capacitance v in =0v 12 pf t14.0 1206
data sheet 2 mbit lpc flash sst49lf020a 29 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 13: lclk waveform (lpc mode) table 15: reliability characteristics symbol parameter minimum specification units test method n end 1 endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t15.0 1206 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. table 16: clock timing parameters (lpc mode) symbol parameter min max units t cyc lclk cycle time 30 ns t high lclk high time 11 ns t low lclk low time 11 ns - lclk slew rate (peak-to-peak) 1 4 v/ns - rst# or init# slew rate 50 mv/ns t16.0 1206 1206 f14.0 0.4 v dd p-to-p (minimum) t cyc t high t low 0.4 v dd 0.3 v dd 0.6 v dd 0.2 v dd 0.5 v dd
30 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 14: reset timing diagram (lpc mode) table 17: reset timi ng parameters, v dd =3.0-3.6v (lpc mode) symbol parameter min max units t prst v dd stable to reset low 1 ms t krst clock stable to reset low 100 s t rstp rst# pulse width 100 ns t rstf rst# low to output float 48 ns t rst 1 rst# high to lframe# low 1 s t rste rst# low to reset during sector-/block-erase or program 10 s t17.0 1206 1. there may be additional latency due tot rste if a reset procedure is performed during a program or erase operation. table 18: read/write cycle timing parameters, v dd =3.0-3.6v (lpc mode) symbol parameter min max units t cyc clock cycle time 30 ns t su data set up time to clock rising 7 ns t dh clock rising to data hold time 0 ns t val 1 1. minimum and maximum times have different loads. see pci spec. clock rising to data valid 2 11 ns t bp byte programming time 20 s t se sector-erase time 25 ms t be block-erase time 25 ms t on clock rising to active (float to active delay) 2 ns t off clock rising to inactive (active to float delay) 28 ns t18.0 1206 clk v dd rst#/init# lframe# lad[3:0] 1206 f15.0 t prst t krst t rstp t rstf t rste sector-/block-erase or program operation aborted t rst
data sheet 2 mbit lpc flash sst49lf020a 31 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 15: output timing parameters (lpc mode) table 19: ac input/output specifications (lpc mode) symbol parameter min max units conditions i oh (ac) switching current high -12 v dd -17.1(v dd -v out ) equation c 1 ma ma 0 < v out 0.3 v dd 0.3 v dd < v out < 0.9 v dd 0.7 v dd < v out < v dd (test point) -32 v dd ma v out = 0.7 v dd i ol (ac) switching current low 16 v dd 26.7 v out equation d 1 ma ma v dd >v out 0.6 v dd 0.6 v dd > v out > 0.1 v dd 0.18 v dd > v out > 0 (test point) 38 v dd ma v out = 0.18 v dd i cl low clamp current -25+(v in +1)/0.015 ma -3 < v in -1 i ch high clamp current 25+(v in -v dd -1)/0.015 ma v dd +4 > v in v dd +1 slewr 2 output rise slew rate 1 4 v/ns 0.2 v dd -0.6 v dd load slewf 2 output fall slew rate 1 4 v/ns 0.6 v dd -0.2 v dd load t19.0 1206 1. see pci spec. 2. pci specification output load is used. t val t off t on 1206 f16.0 lclk lad [3:0] (valid output data) lad [3:0] (float output data) v test v tl v th
32 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 16: input timing parameters (lpc mode) table 20: interface measurement condition parameters (lpc mode) symbol value units v th 1 1. the input test environment is done with 0.1 v dd of overdrive over v ih and v il . timing parameters must be met with no more over- drive than this. v max specified the maximum peak-to-peak wa veform allowed for measuring input timing. production testing may use different voltage values, but must correlate results back to these parameters 0.6 v dd v v tl 1 0.2 v dd v v test 0.4 v dd v v max 1 0.4 v dd v input signal edge rate 1 v/ns t20.0 1206 t su t dh inputs valid 1206 f17.0 lclk lad [3:0] (valid input data) v test v tl v max v th
data sheet 2 mbit lpc flash sst49lf020a 33 ?2006 silicon storage technology, inc. s71206-08-000 5/06 table 21: read cycle timing parameters, v dd =3.0-3.6v (pp mode) symbol parameter min max units t rc read cycle time 270 ns t rst rst# high to row address setup 1 s t as r/c# address set-up time 45 ns t ah r/c# address hold time 45 ns t aa address access time 120 ns t oe output enable access time 60 ns t olz oe# low to active output 0 ns t ohz oe# high to high-z output 35 ns t oh output hold from address change 0 ns t21.0 1206 table 22: program/erase cycle timing parameters, v dd =3.0-3.6v (pp mode) symbol parameter min max units t rst rst# high to row address setup 1 s t as r/c# address setup time 50 ns t ah r/c# address hold time 50 ns t cwh r/c# to write enable high time 50 ns t oes oe# high setup time 20 ns t oeh oe# high hold time 20 ns t oep oe# to data# polling delay 40 ns t oet oe# to toggle bit delay 40 ns t wp we# pulse width 100 ns t wph we# pulse width high 100 ns t ds data setup time 50 ns t dh data hold time 5 ns t ida software id access and exit time 150 ns t bp byte programming time 20 s t se sector-erase time 25 ms t be block-erase time 25 ms t sce chip-erase time 100 ms t22.0 1206 table 23: reset timi ng parameters, v dd =3.0-3.6v (pp mode) symbol parameter min max units t prst v dd stable to reset low 1 ms t rstp rst# pulse width 100 ns t rstf rst# low to output float 48 ns t rst 1 1. there may be additional reset latency due to t rste or t rstc if a reset procedure is performed during a program or erase operation. rst# high to row address setup 1 s t rste rst# low to reset during sector-/block-erase or program 10 s t rstc rst# low to reset during chip-erase 50 s t23.0 1206
34 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 17: reset timing diagram (pp mode) figure 18: read cycle timing diagram (pp mode) v dd rst# addresses r/c# dq 7-0 1206 f18.0 t prst t rstp t rstf t rste row address sector-/block-erase or program operation aborted t rst t rstc chip-erase aborted rst# t rst 1206 f19.0 column address data valid high-z row address column address row address addresses r/c# v ih high-z t rc t as t ah t ah t aa t oe t olz t ohz t oh t as we# oe# dq 7-0
data sheet 2 mbit lpc flash sst49lf020a 35 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 19: write cycle timing diagram (pp mode) figure 20: data# polling timing diagram (pp mode) 1206 f20.0 column address row address data valid rst# addresses r/c# t rst t as t ah t cwh t wp t oes t wph t oeh t dh t ds t ah t as we# oe# dq 7-0 1206 f21.0 addresses r/c# t oep row column we# oe# dq 7 d# d d# d
36 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 21: toggle bit timing diagram (pp mode) figure 22: byte-program timing diagram (pp mode) 1206 f22.0 addresses r/c# t oet row column we# oe# dq 6 d d 5555 5555 2aaa a 14-0 (internal a ms-0 ) r/c# oe# we# dq 7-0 ba internal program starts aa 55 a0 data ba = byte-program address a ms = most significant address 1206 f23.0
data sheet 2 mbit lpc flash sst49lf020a 37 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 23: sector-erase timing diagram (pp mode) figure 24: block-erase timing diagram (pp mode) 5555 5555 5555 2aaa sa x 2aaa a 14-0 (internal a ms-0 ) r/c# oe# we# dq 7-0 internal erase starts aa 55 80 aa 55 30 sa x = sector address 1206 f24.0 5555 5555 5555 2aaa ba x 2aaa a 14-0 (internal a ms-0 ) r/c# oe# we# dq 7-0 internal erase starts aa 55 80 aa 55 50 ba x = block address 1206 f25.0
38 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 25: chip-erase timing diagram (pp mode) figure 26: software id entry and read (pp mode) figure 27: software id exit (pp mode) 5555 5555 5555 2aaa 5555 2aaa a 14-0 (internal a ms-0 ) r/c# oe# we# dq 7-0 internal erase starts aa 55 80 aa 55 10 1206 f26.0 5555 5555 0000 0001 2aaa a 14-0 (internal a ms-0 ) r/c# oe# we# dq 7-0 aa 1206 f27.0 device id bf 55 90 t wp t wph t ida t aa note: device id = 52h for sst49lf020a 5555 5555 2aaa a 14-0 (internal a ms-0 ) r/c# oe# we# dq 7-0 aa 1206 f28.0 55 f0 t ida
data sheet 2 mbit lpc flash sst49lf020a 39 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 28: ac input/output reference waveforms figure 29: a test load example 1206 f29.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <3 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1206 f30.0 to tester to dut c l
40 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 30: read flowchart (lpc mode) figure 31: byte-program flowchart (lpc mode) 1206 f31.0 address: a in read data: d out cycle: 1 read command sequence available for next command 1206 f32.0 address: 5555h write data: aah cycle: 1 address: 2aaah write data: 55h cycle: 2 address: 5555h write data: a0h cycle: 3 address: a in write data: d in cycle: 4 available for next byte wait t bp
data sheet 2 mbit lpc flash sst49lf020a 41 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 32: erase command sequences flowchart (lpc mode) 1206 f33.0 sector-erase command sequence address: 5555h write data: aah cycle: 1 address: 2aaah write data: 55h cycle: 2 address: 5555h write data: 80h cycle: 3 address: 5555h write data: aah cycle: 4 address: 2aaah write data: 55h cycle: 5 sector erased to ffh address: sa x write data: 30h cycle: 6 wait t se available for next command block-erase command sequence address: 5555h write data: aah cycle: 1 address: 2aaah write data: 55h cycle: 2 address: 5555h write data: 80h cycle: 3 address: 5555h write data: aah cycle: 4 address: 2aaah write data: 55h cycle: 5 block erased to ffh address: ba x write data: 50h cycle: 6 wait t be available for next command
42 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 33: software product id command sequences flowchart (lpc mode) 1206 f34.0 software product id entry command sequence wait t ida software product id exit command sequence wait t ida wait t ida address: 5555h write data: aah cycle: 1 address: 2aaah write data: 55h cycle: 2 address: 5555h write data: 90h cycle: 3 address: 5555h write data: aah cycle: 1 address: xxxxh write data: f0h cycle: 1 address: 2aaah write data: 55h cycle: 2 address: 5555h write data: f0h cycle: 3 address: 0001h read data: bfh cycle: 4 address: 0002h read data: cycle: 5 available for next command available for next command available for next command note: x can be v il or v ih , but no other value.
data sheet 2 mbit lpc flash sst49lf020a 43 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 34: byte-program command sequences flowchart (pp mode) 1206 f35.0 start write data: aah address: 5555h write data: 55h address: 2aaah write data: a0h address: 5555h load byte address/byte data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed
44 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 35: wait options flowchart (pp mode) 1206 f36.0 wait t bp , t sce , t be , or t se byte- program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte data# polling program/erase completed program/erase completed read byte is dq 7 = true data? read dq 7 byte- program/erase initiated byte- program/erase initiated
data sheet 2 mbit lpc flash sst49lf020a 45 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 36: software product id command sequences flowchart (pp mode) 1206 f37.0 write data: aah address: 5555h software product id entry command sequence write data: 55h address: 2aaah write data: 90h address: 5555h wait t ida read software id write data: aah address: 5555h software product id exit command sequence write data: 55h address: 2aaah write data: f0h address: 5555h write data: f0h address: xxh return to normal operation wait t ida wait t ida return to normal operation
46 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 37: erase command sequence flowchart (pp mode) 1206 f38.0 write data: aah address: 5555h chip-erase command sequence write data: 55h address: 2aaah write data: 80h address: 5555h write data: 55h address: 2aaah write data: 10h address: 5555h write data: aah address: 5555h wait t sce chip erased to ffh write data: aah address: 5555h sector-erase command sequence write data: 55h address: 2aaah write data: 80h address: 5555h write data: 55h address: 2aaah write data: 30h address: sa x write data: aah address: 5555h wait t se sector erased to ffh write data: aah address: 5555h block-erase command sequence write data: 55h address: 2aaah write data: 80h address: 5555h write data: 55h address: 2aaah write data: 50h address: ba x write data: aah address: 5555h wait t be block erased to ffh
data sheet 2 mbit lpc flash sst49lf020a 47 ?2006 silicon storage technology, inc. s71206-08-000 5/06 product ordering information valid combinations for sst49lf020a SST49LF020A-33-4C-WHE sst49lf020a-33-4c-nhe note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. device speed suffix1 suffix2 sst49 l f0x0 a - xxx -x x -xx x environmental attribute e 1 = non-pb package modifier h = 32 leads package type n = plcc w = tsop (type 1, die up, 8mm x 14mm) operating temperature c = commercial = 0c to +85c minimum endurance 4 = 10,000 cycles serial access clock frequency 33 = 33 mhz device density 020 = 2 mbit voltag e rang e l = 3.0-3.6v product series 49 = lpc firmware flash 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?.
48 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 packaging diagrams figure 38: 32-lead plastic lead chip carrier (plcc) sst package code: nh .040 .030 .021 .013 .530 .490 .095 .075 .140 .125 .032 .026 .032 .026 .029 .023 .453 .447 .553 .547 .595 .585 .495 .485 .112 .106 .042 .048 .048 .042 .015 min. top view side view bottom view 1 232 .400 bsc 32-plcc-nh-3 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (max/min). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. 4. coplanarity: 4 mils. .050 bsc .050 bsc optional pin #1 identifier .020 r. max. r. x 30?
data sheet 2 mbit lpc flash sst49lf020a 49 ?2006 silicon storage technology, inc. s71206-08-000 5/06 figure 39: 32-lead thin small outline package (tsop) 8mm x 14mm sst package code: wh 32-tsop-wh-7 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm pin # 1 identifier 12.50 12.30 14.20 13.80 0.70 0.50 8.10 7.90 0.27 0.17 0. 50 bsc 1.05 0.95 0.15 0.05 0.70 0.50 0?- 5? detail
50 data sheet 2 mbit lpc flash sst49lf020a ?2006 silicon storage technology, inc. s71206-08-000 5/06 table 24: revision history number description date 00 ? initial release sep 2001 01 ? added sst49lf030a to the data sheet jan 2002 02 ? added sst49lf020a to the data sheet may 2002 03 ? corrected lframe and ce# test conditions for standby v dd current in table 18 jul 2002 04 ? removed sst49lf040a from the data sheet ? added support for bottom address space to sst49lf030a nov 2002 05 ? moved sst49lf030a from this data sheet (s71206) to data sheet s71234 ? moved sst49lf080a from this data sheet (s71206) to data sheet s71235 ? changed status from ?preliminary specifications? to ?data sheet? ? added switching inputs into test conditions for i dd apr 2003 06 ? 2004 data book ? added non-pb mpns and removed footnote. (see page 47) dec 2003 07 ? added statement that non-pb devices are rohs compliant to features section ? updated surface mount solder reflow temperature information ? added footnote to product ordering information section ? removed leaded part numbers jan 2006 08 ? updated table 5 on page 12 may 2006 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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